Low Power, Multi-Gigabit DRAM Cell Design Issues Using SOI Technologies
نویسندگان
چکیده
Silicon On Insulator (SOI) can leverage a lot of new advantages for circuit designers compared to conventional bulk technology. In particular, the improved S-factor and reduced junction capacitance make it very appealing for next generation low power, high performance DRAM systems. However, the benefits of the SOI technology do not come entirely for free. In this project, we characterized the key parameters of SOI devices in regards to DRAM applications, and simulated various control schemes used in DRAMs for different SOI technologies. As expected our results show a large improvement in bit line capacitance for the SOI devices compared to the bulk devices. A comparison of the different SOI technologies shows a significant overall advantage of using fully depleted SOI devices compared to partially depleted SOI in terms of both power and performance.
منابع مشابه
Fully Depleted SOI MOSFETs for DRAM
SOI technology has received high attention for the future high density DRAM applications. The two major requirements in any DRAM technology are long retention time and high charging efficiency. This paper discusses the disadvantages of using bulk silicon and Partially Depleted SOI devices in these terms. It is shown that a DRAM cell built with fully depleted SOI MOSFETs can store data for a lon...
متن کاملZ-FET as capacitor-less eDRAM cell for high density integration
2D numerical simulations are used to demonstrate the Z-FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption ...
متن کاملSOI technology for the GHz era
Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we de...
متن کاملTechnological Innovations to Advance Scalability and Interconnects in Bulk and SOI
Introduction With technology scaling rapidly, there is increased need for improved performance. While improved performance can be achieved with lower threshold voltages, leakage will be a major issue at technologies below 0.1μm. Interconnect scaling is not expected to keep up with component scaling, resulting in higher capacitance losses and challenges in signal routing. We consider how scaling...
متن کاملA Low Power Full Adder Cell based on Carbon Nanotube FET for Arithmetic Units
In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...
متن کامل